This invention relates in general to semiconductor device failure analysis methods and in particular, to a method of identifying a weakest interface where delamination is most likely to occur in a multi-layer dielectric film stack.
Multi-layer dielectric film stacks consisting of, for example, a spin-on glass ("SOG") layer sandwiched between plasma-enhanced chemical vapor deposition ("PECVD") oxide layers are commonly used as intermetal dielectric ("IMD") stacks in integrated circuit ("IC") semiconductor manufacturing. One problem with non-etchbacked PECVD-Ox/SOG/PECVD-Ox stacks, particularly for large semiconductor die, is delamination of the IMD stack at the SOG layer.
As an example, multi-level metallization is important for the performance and circuit density of Application Specific Integrated Circuits ("ASICs"). In ASIC designs, large dies having extensive areas without metallization are not uncommon, and these areas are known to delaminate when non-etchbacked IMD stacks are used. In order to study delamination mechanisms in such multi-layer IMD stacks, it is useful to know the weakest interface where delamination is most likely to occur in such multi-layer IMD stacks.